January 29, 2025
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Many novice engineers, especially those in small-signal or low-power fields, may be unfamiliar with the Miller effect. They often assume a MOSFET turns on as simply as toggling a digital IO signal, but the reality is more complex.
During the turn-on process, the gate-source voltage (Vgs) transitions through three distinct stages. The reason this characteristic waveform isn’t always observed in small-signal MOSFETs is due to an insufficiently expanded oscilloscope timebase. When zoomed in adequately, the Miller plateau becomes clearly visible.
The following analysis focuses on the formation of the Miller plateau in a hard-switching application with an inductive load.
t0: The MOSFET is off. Vgs is 0V, and the drain-source voltage (Vds) is at the supply level, VDD. No power is delivered to the load.
t1: Vgs reaches the threshold voltage (Vth), typically around 2-3V, though this value can vary between devices. The drain-source on-resistance (Rds(on)) begins to decrease from a very high value, allowing the drain current (Id) to rise. Consequently, Vds starts to decrease gradually.
t2: Rds(on) reaches its minimum value, and the drain current (Id) stabilizes at its maximum. The Vds voltage now begins to fall rapidly, influenced by the load and the gate drive current, eventually approaching zero as the MOSFET becomes fully enhanced.
The key question is: why does the Vgs voltage plateau starting at t2?
The answer lies in the gate-drain capacitance (Cgd). Beginning at t2, the voltage across Cgd (Vgd) undergoes a large swing from VDD down to nearly 0V (with the source as ground reference). During this rapid voltage transition, the gate drive current is diverted to charge Cgd. If the rate of this charging current matches the rate of the Vgd collapse, the Vgs voltage remains constant, forming the characteristic “Miller plateau.”
The plateau duration (t2-t3) is typically short due to the low Rds(on). Once Vgd stabilizes near 0V, the gate current resumes charging the capacitances, allowing Vgs to climb to the final drive voltage.
In summary, the Miller plateau is a direct result of the capacitive coupling between the drain voltage swing and the gate, which effectively “pins” the gate voltage during the critical period when Vds is falling.
Power loss in a MOSFET is calculated as P = Vds × Id. Significant losses occur during the switching transitions, specifically:
t1-t2: Vds is still high while Id is rising linearly, resulting in high instantaneous power dissipation.
t2-t3 (Miller Plateau): Id is at its maximum while Vds has not yet reached its minimum, making this a period of very high power loss.
Therefore, the primary strategy for reducing switching losses is to shorten the critical t1-t3 interval. This requires a faster Vgs rise time, which is achieved by increasing the current available to charge the gate capacitances (Cgs and Cgd).
For example, consider a 100V, 2mΩ MOSFET. To minimize switching losses, the first step is to select a device with low input capacitance (Ciss). If the MOSFET is already chosen, the only option is to use a strong gate drive current.
Suppose the selected MOSFET has a total gate charge (Qg) of 169nC. With a 2A gate drive current, the theoretical switching time is:
This suggests the entire Vgs rise, including the Miller plateau, could theoretically complete in under 100ns. However, this is an ideal calculation. In practice, factors like the gate resistor’s current limiting and the dynamic voltage across the Miller capacitance will extend the actual switching time. A robust driver is essential to overcome these limitations and achieve fast, efficient switching.
